Integrated circuits include several conductors distributed across the topography of their substrates. The conductors are isolated from each other, and from underlying conductive elements, with a dielectric material. Interconnect lines serve to electrically connect two or more components (e.g. conductors) within a system.
Conductor-to-conductor capacitance (CLL), or parasitic capacitance, is determined as follows:CLL=∈TcL/Td2,wherein ∈ is the permittivity of the dielectric material between the conductors, Tc is the conductor thickness, L is the conductor length, and Td2 is the distance in which each conductor is dielectrically spaced from other conductors. Thus, as device dimensions and component spacing continues to shrink to meet increasing demands for smaller electronic devices, parasitic capacitance increases. This is undesirable because parasitic capacitance contributes to effects such as RC delay, power dissipation, and capacitively couples signals, also known as cross-talk. Therefore, it would be desirable to provide MOSFET structures having lower parasitic capacitance between conductors, as well as methods for making such MOSFET structures.